ICTCampus
A/L ICT syllabus
Grade 1222 periods

Introduction to Computer

Explores the evolution of computing devices, so as to be able to describe and compare the performance of modern computers

  1. Join this class

    Exam objectives

    • Describe generations 1G-4G of computers with their defining technology and features, in tabular form
    • Classify computers by technology (analog/digital), purpose (general/special) and size (super/mainframe/mini/micro, incl. mobile devices)

    Important areas to cover

    • "Complete the generations-of-computers table" is a classic structured question
    • Classify-by-example MCQs (e.g. what class a smartphone falls into) are common

    Lesson content not added yet.

  2. Join this class

    Exam objectives

    • Identify input devices, distinguishing direct-entry from keyboard-entry, and their interfaces
    • Identify output devices and their features (CRT/TFT/LED monitors, dot-matrix/inkjet/laser/3D printers, plotters)
    • Categorise storage devices and state the advantages of direct-entry input over keyboard-entry input

    Important areas to cover

    • Matching a device to input/output/storage is heavily tested in MCQs
    • "Advantages of direct-entry input over keyboard entry" is a recurring short-answer question

    Lesson content not added yet.

  3. Join this class

    Exam objectives

    • Draw and label the Von-Neumann architecture (CU, ALU, memory, I/O, data and control buses)
    • Describe the stored-program concept and the fetch-execute cycle
    • Explain why multi-core processors are needed

    Important areas to cover

    • Drawing the Von-Neumann diagram from memory is one of the most frequently repeated essay/structured tasks in the whole syllabus
    • Listing the fetch-execute cycle steps in order is a common short-answer question

    Notes

    The stored-program concept

    Von Neumann's idea is that instructions and data live in the same memory, in the same form. Before it, changing a machine's program meant rewiring it. After it, a program is just data you load — which is why one computer can run a spreadsheet and a game.

    The five parts of the architecture

    - Control unit (CU) — fetches and decodes instructions, and raises the control signals that make everything else act - Arithmetic and logic unit (ALU) — does the arithmetic and the comparisons - Main memory — holds instructions and data together, each in a numbered address - Input and output — how data gets in and out - Buses — the address bus (one direction, CPU to memory), the data bus (both directions) and the control bus (both directions)

    The CU and the ALU together with the registers make up the CPU. A full-mark diagram has all five parts and all three buses, with arrowheads showing that the address bus is one-directional and the other two are not.

    The registers

    - PC, the program counter — the address of the next instruction - MAR, the memory address register — the address currently on the address bus - MDR, the memory data register — whatever is in transit to or from memory. Some textbooks write MBR; it is the same register - CIR, the current instruction register — the instruction being carried out right now - ACC, the accumulator — where the ALU keeps the working value

    The cycle itself

    Fetch is the same four steps for every instruction, without exception:

    • MAR ← PC
    • MDR ← contents of the address held in MAR
    • PC ← PC + 1
    • CIR ← MDR

    Decode is next: the control unit splits the instruction now in CIR into an opcode and an address part, and works out which control signals to raise.

    Execute is last, and is the only phase that depends on which instruction it is.

    Two places marks are lost

    The PC is incremented during the fetch, not after the instruction has run. That is exactly why a jump instruction has to overwrite the PC rather than add to it: by the time the jump executes, the PC has already moved on.

    MDR carries data in both directions. On a LOAD it brings a value in from memory; on a STORE it carries the accumulator's value out to memory. Describing it as an input-only register is wrong.

    Why multi-core processors are needed

    Everything above runs one instruction at a time, and every instruction and every piece of data has to travel the same path between CPU and memory. That single path is the von Neumann bottleneck: past a point, making the CPU faster stops helping because it is waiting on memory. Several complete cores, each with its own fetch-execute machinery and sharing the memory, is one answer to it.

    Try it — step one instruction through the cycle

    The program below adds the number at address 5 to the number at address 6 and stores the answer at address 7. Every instruction takes the same four fetch steps and one decode step. Only the execute steps differ.

    FetchDecodeExecuteStep 1 of 29

    Registers

    PC
    0
    MAR
    0
    MDR
    empty
    CIR
    empty
    ACC
    0

    Hover a register name to see what it is for.

    Main memory

    1. 0LOAD 5PC
    2. 1ADD 6
    3. 2STORE 7
    4. 3HALT
    5. 4—
    6. 512
    7. 630
    8. 70

    Addresses 0–3 hold the program. 5–7 hold its data.

    MAR ← PCAddress bus

    The address of the next instruction (0) is copied from the program counter into the memory address register, and put on the address bus.

  4. Join this class

    Exam objectives

    • Explain the need for a memory hierarchy and its comparison criteria (access time, capacity, cost)
    • Compare volatile memory (registers, cache, RAM incl. SRAM/DRAM/SDRAM) and non-volatile memory (ROM/PROM/EPROM/EEPROM, secondary storage)
    • Compare memory types by access time, cost per MB, capacity and physical arrangement of data

    Important areas to cover

    • Comparison tables of RAM vs ROM vs cache are a recurring structured question
    • "Why is a memory hierarchy needed" is a regular short-essay question

    Lesson content not added yet.